IS61LV6416

2022-12-20 来源：年旅网

IS61LV6416IS61LV6416L64K x 16 HIGH-SPEED CMOS STATIC RAMWITH 3.3V SUPPLY

FEATURES

•High-speed access time: 8, 10, 12 ns•CMOS low power operation— 61LV6416:

75 mW (typical) operating current 0.5 mW (typical) standby current— 61LV6416L:

65 mW (typical) operating current 50 µW (typical) standby current•TTL compatible interface levels•Single 3.3V power supply

•Fully static operation: no clock or refreshrequired

•Three state outputs

•Data control for upper and lower bytes•Industrial temperature available

ISSIOCTOBER 2003

DESCRIPTION

The ISSI IS61LV6416/IS61LV6416L is a high-speed,

1,048,576-bit static RAM organized as 65,536 words by 16bits. It is fabricated using ISSI's high-performance CMOStechnology. This highly reliable process coupled withinnovative circuit design techniques, yields access timesas fast as 8 ns with low power consumption.

When CE is HIGH (deselected), the device assumes astandby mode at which the power dissipation can bereduced down with CMOS input levels.

Easy memory expansion is provided by using ChipEnable and Output Enable inputs, CE and OE. The activeLOW Write Enable (WE) controls both writing and readingof the memory. A data byte allows Upper Byte (UB) andLower Byte (LB) access.

The IS61LV6416/IS61LV6416L is packaged in the JEDECstandard 44-pin 400-mil SOJ, 44-pin TSOP-II, and 48-pinmini BGA (6mm x 8mm).

FUNCTIONAL BLOCK DIAGRAM

A0-A15DECODER64K x 16MEMORY ARRAYVDDGNDI/O0-I/O7Lower ByteI/O8-I/O15Upper ByteI/ODATACIRCUITCOLUMN I/OCEOEWEUBLBCONTROLCIRCUITCopyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabilityarising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on anypublished information and before placing orders for products.

Integrated Silicon Solution, Inc.Rev. C10/14/03

IS61LV6416IS61LV6416L

PIN CONFIGURATIONS44-Pin SOJ (K)

A15A14A13A12A11CEI/O0I/O1I/O2I/O3VDDGNDI/O4I/O5I/O6I/O7WEA10A9A8A7NC1234567891011121314151617181920212244434241403938373635343332313029282726252423A0A1A2OEUBLBI/O15I/O14I/O13I/O12GNDVDDI/O11I/O10I/O9I/O8NCA3A4A5A6NCISSI44-Pin TSOP-II (T)

A15A14A13A12A11CEI/O0I/O1I/O2I/O3VDDGNDI/O4I/O5I/O6I/O7WEA10A9A8A7NC1234567891011121314151617181920212244434241403938373635343332313029282726252423®

A0A1A2OEUBLBI/O15I/O14I/O13I/O12GNDVDDI/O11I/O10I/O9I/O8NCA3A4A5A6NC48-Pin mini BGA(6mm x 8mm) (B)

1 2 3 4 5 6PIN DESCRIPTIONS

A0-A15I/O0-I/O15CEOEWELBUBNCVDDGND

Address InputsData Inputs/OutputsChip Enable InputOutput Enable InputWrite Enable Input

Lower-byte Control (I/O0-I/O7)Upper-byte Control (I/O8-I/O15)No ConnectionPowerGround

ABCDEFGHLBI/O8I/O9GNDVDDI/O14I/O15NCOEUBI/O10I/O11I/O12I/O13NCA8A0A3A5NCNCA14A12A9A1A4A6A7NCA15A13A10A2CEI/O1I/O3I/O4I/O5WEA11NCI/O0I/O2VDDGNDI/O6I/O7NC2Integrated Silicon Solution, Inc. Rev.C10/14/03

IS61LV6416IS61LV6416L

TRUTH TABLE

Mode

Not SelectedOutput DisabledRead

WEXHXHHHLLL

CEHLLLLLLLL

OEXHXLLLXXX

LBXXHLHLLHL

UBXXHHLLHLL

I/O PIN

I/O0-I/O7I/O8-I/O15High-ZHigh-ZHigh-ZDOUTHigh-ZDOUTDINHigh-ZDIN

High-ZHigh-ZHigh-ZHigh-ZDOUTDOUTHigh-ZDINDIN

ISSIVDD CurrentISB1, ISB2

ICC

1234WriteICC

ABSOLUTE MAXIMUM RATINGS(1)

SymbolVTERMTSTGPTIOUT

Parameter

Terminal Voltage with Respect to GNDStorage TemperaturePower Dissipation

DC Output Current (LOW)

Value

–0.5 to VDD+0.5–65 to +150

1.520

UnitV°CWmA

567VDD (12 ns)3.3V ± 10%3.3V ± 10%

Note:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation ofthe device at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect reliability.

OPERATING RANGE

Range

CommercialIndustrial

Ambient Temperature

0°C to +70°C–40°C to +85°C

VDD (8,10 ns)3.3V+10%,-5%3.3V+10%,-5%

8910Max.—0.4VDD + 0.30.822

UnitVVVVµAµA

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

SymbolVOHVOLVIHVILILIILO

Parameter

Output HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW Voltage(1)Input LeakageOutput Leakage

GND ≤ VIN ≤ VDD

GND ≤ VOUT ≤ VDD, Outputs DisabledTest Conditions

VDD = Min., IOH = –4.0 mAVDD = Min., IOL = 8.0 mA

Min.2.4—2–0.3–2–2

1112Notes:

1.VIL (min.) = –2.0V for pulse width less than 10 ns.

Integrated Silicon Solution, Inc.Rev.C10/14/03

IS61LV6416IS61LV6416L

IS61LV6416

POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

SymbolParameterICCVDD Dynamic OperatingSupply CurrentTTL Standby Current(TTL Inputs)CMOS StandbyCurrent (CMOS Inputs)Test ConditionsVDD = Max.,IOUT = 0 mA, f = fMAXVDD = Max.,VIN = VIH or VILCE ≥ VIH , f = 0VDD = Max.,CE ≥ VDD – 0.2V,VIN ≥ VDD – 0.2V, orVIN ≤ 0.2V, f = 0Com.Ind.typ.(2)Com.Ind.Com.Ind.typ.(2)-8 nsMin.Max.————————14015010515205100.5-10 nsMin.Max.————————1201309515205100.5ISSI-12 nsMin.Max.————————1001107515205100.5®

UnitmAISB1mAISB2mANote:

1.At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% Tested.

IS61LV6416L

POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

SymbolParameterICCVDD Dynamic OperatingSupply CurrentTTL Standby Current(TTL Inputs)CMOS StandbyCurrent (CMOS Inputs)Test ConditionsVDD = Max.,IOUT = 0 mA, f = fMAXVDD = Max.,VIN = VIH or VILCE ≥ VIH , f = 0VDD = Max.,CE ≥ VDD – 0.2V,VIN ≥ VDD – 0.2V, orVIN ≤ 0.2V, f = 0Com.Ind.typ.(2)Com.Ind.Com.Ind.typ.(2)-8 nsMin.Max.————————10011075152011.50.05-10 nsMin.Max.————————9510570152011.50.05UnitmAISB1mAISB2mANote:

1.At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% Tested.

CAPACITANCE(1)

SymbolCINCOUT

ParameterInput CapacitanceInput/Output Capacitance

ConditionsVIN = 0VVOUT = 0V

Max.68

UnitpFpF

Note:

1.Tested initially and after any design or process changes that may affect these parameters.

4Integrated Silicon Solution, Inc. Rev.C10/14/03

IS61LV6416IS61LV6416L

AC TEST CONDITIONS

Parameter

Input Pulse Level

Input Rise and Fall TimesInput and Output Timingand Reference LevelOutput Load

Unit0V to 3.0V3 ns1.5VSee Figures 1a and 1b

ISSI®

123319 Ω3.3VAC TEST LOADS

319 Ω3.3V45 pFIncludingjig andscope353 ΩOUTPUT30 pFIncludingjig andscope353 ΩOUTPUT567Figure 1a.Figure 1b.

READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

SymbolParameterRead Cycle TimeAddress Access TimeOutput Hold TimeCE Access TimeOE Access TimeOE to High-Z OutputOE to Low-Z OutputCE to High-Z OutputCE to Low-Z OutputLB, UB Access TimeLB, UB to High-Z OutputLB, UB to Low-Z Output-8 nsMin.Max.8—3———003—00—8—855—4—64—-10 nsMin.Max.10—3———003—00—10—1055—5—65—-12 nsMin.Max.12—3———003—00—12—1266—6—66—UnitnsnsnsnsnsnsnsnsnsnsnsnstRCtAAtOHAtACEtDOEtHZOE(2)tLZOE(2)tHZCE(2tLZCE(2)tBAtHZBtLZB89101112Notes:

1.Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V andoutput loading specified in Figure 1a.

2.Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.3.Not 100% tested.

Integrated Silicon Solution, Inc.Rev.C10/14/03

IS61LV6416IS61LV6416L

AC WAVEFORMS

READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = VIL, UB or LB = VIL)

t RCADDRESSISSI®

t AAt OHADOUTPREVIOUS DATA VALIDt OHADATA VALIDREAD1.epsREAD CYCLE NO. 2(1,3)

tRCADDRESStAAtOHAOEtDOEtHZOECEtLZCEtLZOEtACEtHZCELB, UBtBAtHZB DATA VALIDDOUTHIGH-ZtLZBNotes:

1.WE is HIGH for a Read Cycle.

2.The device is continuously selected. OE, CE, UB, or LB = VIL.3.Address is valid prior to or coincident with CE LOW transition.

6Integrated Silicon Solution, Inc. Rev.C10/14/03

IS61LV6416IS61LV6416L

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

SymbolParameterWrite Cycle TimeCE to Write EndAddress Setup Timeto Write EndAddress Hold from Write EndAddress Setup TimeLB, UB Valid to End of WriteWE Pulse Width (OE = HIGH/LOW)Data Setup to Write EndData Hold from Write EndWE LOW to High-Z OutputWE HIGH to Low-Z Output-8 nsMin.Max.868007660—3—————————4—-10 nsMin.Max.1088008860—3—————————5—-12 nsMin.Max.1299009960—3—————————6—ISSIUnitnsnsnsnsnsnsnsnsnsnsns®

tWCtSCEtAWtHAtSAtPBWtPWE1/tPWE2tSDtHDtHZWE(2)tLZWE(2)123456789101112Notes:

1.Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V andoutput loading specified in Figure 1a.

2.Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3.The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states toinitiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to therising or falling edge of the signal that terminates the write.

Integrated Silicon Solution, Inc.Rev.C10/14/03

IS61LV6416IS61LV6416L

WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)

ISSIt WC®

ADDRESSVALID ADDRESSt SACEt SCEt AWt PWE1t PWE2t PBWt HAWEUB, LBt HZWEDOUTDATA UNDEFINEDHIGH-Zt LZWEt SDDINt HDDATAIN VALIDUB_CEWR1.eps8Integrated Silicon Solution, Inc. Rev.C10/14/03

IS61LV6416IS61LV6416L

WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)t WCADDRESSVALID ADDRESSISSIt HA®

12OECELOWt AWt PWE1WE34t LZWEHIGH-Zt SAUB, LBt PBWt HZWEDOUTDATA UNDEFINED56UB_CEWR2.epst SDDINt HDDATAIN VALIDWRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

t WCADDRESSOECEVALID ADDRESS78t HALOW9LOWt AWt PWE2WE10t LZWEt SAUB, LBt PBWt HZWE1112UB_CEWR3.epsDOUTDATA UNDEFINEDHIGH-Zt SDDINt HDDATAIN VALIDIntegrated Silicon Solution, Inc.Rev.C10/14/03

IS61LV6416IS61LV6416L

WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write)(1,3)

t WCADDRESSADDRESS 1ISSIt WCADDRESS 2®

OEt SACELOWWEt HAt SAt PBWt PBWWORD 2t HAUB, LBWORD 1t HZWEDOUTDATA UNDEFINEDHIGH-Zt LZWEt HDDATAINVALIDt SDDINt SDDATAINVALIDt HDUB_CEWR4.epsNotes:1.The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must bein valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing isreferenced to the rising or falling edge of the signal that terminates the Write.

2.Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.

3.WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.

10Integrated Silicon Solution, Inc. Rev.C10/14/03

IS61LV6416IS61LV6416L

DATA RETENTION SWITCHING CHARACTERISTICS

SymbolParameterVDD for Data RetentionData Retention CurrentData Retention Setup TimeRecovery TimeTest ConditionSee Data Retention WaveformVDD = 2.0V, CE ≥ VDD – 0.2VSee Data Retention WaveformSee Data Retention WaveformOISSIOptionsIS61LV6416IS61LV6416LMin.2.0——0Typ.(1)—0.50.05——Max.3.6101.5——UnitVmAnsns®

VDRIDR1234tSDRtRDRtRCNote 1: Typical values are measured at VDD = 3.0V, TA = 25C and not 100% tested.DATA RETENTION WAVEFORM (CE Controlled)

5tSDRVDDData Retention ModetRDR67CE ≥ VDD - 0.2VVDRCEGND89101112Integrated Silicon Solution, Inc.Rev.C10/14/03

IS61LV6416IS61LV6416L

IS61LV6416

ORDERING INFORMATION

Speed (ns)

888101010101010121212121212

Order Part No.IS61LV6416-8TIS61LV6416-8BIIS61LV6416-8TIIS61LV6416-10TIS61LV6416-10BIS61LV6416-10KIS61LV6416-10BIIS61LV6416-10TIIS61LV6416-10KIIS61LV6416-12BIS61LV6416-12TIS61LV6416-12KIS61LV6416-12BIIS61LV6416-12TIIS61LV6416-12KI

Package

Plastic TSOP

mini BGA(6mm x 8mm)Plastic TSOP

Plastic TSOP

mini BGA(6mm x 8mm)400-mil Plastic SOJmini BGA(6mm x 8mm)Plastic TSOP400-mil Plastic SOJmini BGA(6mm x 8mm)Plastic TSOP400-mil Plastic SOJmini BGA(6mm x 8mm)Plastic TSOP400-mil Plastic SOJTemperature Range

ISSICommercial (0°C to +70°C )Industrial (-40°C to +85°C )Industrial (-40°C to +85°C )Commercial (0°C to +70°C )Commercial (0°C to +70°C )Commercial (0°C to +70°C )Industrial (-40°C to +85°C )Industrial (-40°C to +85°C )Industrial (-40°C to +85°C )Commercial (0°C to +70°C )Commercial (0°C to +70°C )Commercial (0°C to +70°C )Industrial (-40°C to +85°C )Industrial (-40°C to +85°C )Industrial (-40°C to +85°C )

IS61LV6416L

ORDERING INFORMATION

Speed (ns)

888810101010

Order Part No.IS61LV6416L-8TIS61LV6416L-8BIIS61LV6416L-8TIIS61LV6416L-8KIIS61LV6416L-10TIS61LV6416L-10BIIS61LV6416L-10TIIS61LV6416L-10KI

Package

Plastic TSOP

mini BGA(6mm x 8mm)Plastic TSOP400-mil Plastic SOJPlastic TSOP

mini BGA(6mm x 8mm)Plastic TSOP400-mil Plastic SOJTemperature RangeCommercial (0°C to +70°C )Industrial (-40°C to +85°C )Industrial (-40°C to +85°C )Industrial (-40°C to +85°C )Commercial (0°C to +70°C )Industrial (-40°C to +85°C )Industrial (-40°C to +85°C )Industrial (-40°C to +85°C )

12Integrated Silicon Solution, Inc. Rev.C10/14/03

PACKAGING INFORMATION

Mini Ball Grid Array

Package Code: B (48-pin)

Top View1 2 3 4 5 6ISSI

Bottom Viewφ b (48x)®

6 5 4 3 2 1ABCDDEFGHD1eABCDEFGHeEE1A2SEATING PLANEA1ANotes:1. Controlling dimensions are in millimeters.mBGA - 6mm x 8mmMILLIMETERSSym.N0.LeadsAA1A2DD1EE1eb— 0.240.607.905.90mBGA - 8mm x 10mmINCHESMin.Typ.Max.Sym.N0.LeadsMILLIMETERMin.Typ.Max. 48— 0.240.609.907.90—————1.200.30—10.108.10—INCHESMin.Typ.Max.Min.Typ.Max.48—————1.200.30—8.106.10—0.0090.0240.3110.232 — ————0.0470.012—0.3190.240AA1A2DD1EE1eb — ————0.0470.012—0.3980.3190.0090.0240.3900.3115.25 BSC3.75 BSC0.75 BSC0.300.350.400.207 BSC0.148 BSC0.030 BSC0.0120.0140.0165.25 BSC3.75 BSC0.75 BSC0.300.350.400.207 BSC0.148 BSC0.030 BSC0.0120.0140.016Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.D01/15/03

PACKAGING INFORMATION

K-400 mil SOJ PACKAGE OUTLINEISSI

Notes:1. Controlling dimension: millimeters.2. BSC = Basic lead spacing between centers.3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.4. Reference document: JEDEC MS-027.®

N N/2+1E1E1N/2DASEATING PLANEbCA2eBA1E2 400-mil Plastic SOIC (J-bend) (K)Ref. Std. MS-0272832No. Leads (N) inch mm inch mmSymbolMinMaxMinMaxMinMaxMinMaxA0.1280.1483.2503.7500.1281.0483.2503.750A1A2BbCDEE1E2e0.0250.0820.0150.0260.0070.7200.4350.395——0.0200.0320.0130.7300.4450.4050.6352.0800.3800.6600.18018.2911.0510.03——0.5100.8100.33018.5411.3010.290.0250.0820.0150.0260.0070.8200.4350.395——0.0200.0320.0130.8300.4450.4050.6352.0800.3800.6600.18020.8211.0510.03——0.5100.8100.33021.0811.3010.2936 inchMinMax0.1281.0480.0250.0820.0150.0260.0070.9200.4350.395——0.0200.0320.0130.9300.4450.405 mmMinMax3.2503.7500.6352.0800.3800.6600.18023.3711.0510.03——0.5100.8100.33023.6211.3010.29 0.370 BSC 0.050 BSC9.40 BSC1.27 BSC 0.370 BSC 0.050 BSC9.40 BSC1.27 BSC 0.370 BSC 9.40 BSC 0.050 BSC 1.27 BSCCopyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.E10/03/02

PACKAGING INFORMATION

ISSI

44 inchMinMax0.1281.0480.0250.0820.0150.0260.0071.1200.4350.395——0.0200.0320.0131.1300.4450.405®

400-mil Plastic SOIC (J-bend) (K)Ref. Std. MS-0274042No. Leads (N) inch mm inch mmSymbolMinMaxMinMaxMinMaxMinMaxA0.1280.1483.2503.7500.1281.0483.2503.750A1A2BbCDEE1E2e0.0250.0820.0150.0260.0071.0200.4350.395——0.0200.0320.0131.0300.4450.4050.6352.0800.3800.6600.18025.9111.0510.03——0.5100.8100.33026.1611.3010.290.0250.0820.0150.0260.0071.0700.4350.395——0.0200.0320.0131.0800.4450.4050.6352.0800.3800.6600.18027.1811.0510.03——0.5100.8100.33027.4311.3010.29 mmMinMax3.2503.7500.6352.0800.3800.6600.18028.4511.0510.03——0.5100.8100.33028.7011.3010.29 0.370 BSC 0.050 BSC9.40 BSC1.27 BSC 0.370 BSC 0.050 BSC9.40 BSC1.27 BSC 0.370 BSC 9.40 BSC 0.050 BSC 1.27 BSCCopyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.

2Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. E10/03/02

PACKAGING INFORMATION

Plastic TSOPPackage Code: T (Type II)ISSI

Notes:1.Controlling dimension: millimieters,unless otherwise specified.2.BSC = Basic lead spacingbetween centers.3.Dimensions D and E1 do notinclude mold flash protrusions andshould be measured from thebottom of the package.4.Formed leads shall be planar withrespect to one another within0.004 inches at the seating plane.®

NN/2+1E1E1DN/2ZDASEATING PLANE.ebA1LαCSymbolRef. Std.No. Leads (N)324450A—1.20—0.047—1.20—0.047—1.20—0.047A10.050.150.0020.0060.050.150.0020.0060.050.150.0020.006b0.300.520.0120.0200.300.450.0120.0180.300.450.0120.018C0.120.210.0050.0080.120.210.0050.0080.120.210.0050.008D20.8221.080.8200.83018.3118.520.7210.72920.8221.080.8200.830E110.0310.290.3910.40010.0310.290.3950.40510.0310.290.3950.405E11.5611.960.4510.46611.5611.960.4550.47111.5611.960.4550.471e1.27 BSC 0.050 BSC 0.80 BSC0.032 BSC0.80 BSC 0.031 BSCL0.400.600.0160.0240.410.600.0160.0240.400.600.0160.024ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REFα0°5°0°5°0°5°0°5°0°5°0°5°MillimetersMinMaxInchesMinMaxPlastic TSOP (T - Type II)MillimetersInchesMinMaxMinMaxMillimetersMinMaxInchesMinMaxCopyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev.F06/18/03

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IS61LV6416