实验电路结构图及芯片引脚对应表
数码8数码7数码6数码5数码4数码3数码2数码1扬声器译码器译码器译码器译码器译码器译码器译码器译码器PIO19-PIO16PIO23-PIO20PIO27-PIO24PIO31-PIO28PIO35-PIO32PIO39-PIO36PIO43-PIO40PIO47-PIO44D8D7D6D5D4D3D2D1SPEAKERFPGA/CPLD目标芯片PIO7D16PIO6D15PIO5D14PIO4D13PIO3D12PIO2D11HEXHEX键1PIO7--PIO2PIO11-PIO8PIO15-PIO12键8键7键6键5键4键3键2实验电路结构图NO.0
附图2-2 实验电路结构图NO.0
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附图2-3 实验电路结构图NO.1
附图2-4 实验电路结构图NO.2
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87654321ÑïÉùÆ÷PIO19-PIO16PIO23-PIO20PIO27-PIO24PIO31-PIO28PIO35-PIO32PIO39-PIO36PIO43-PIO40PIO47-PIO44D8PIO15D7PIO14D6PIO13D5PIO12D4PIO11D3PIO10D2PIO9D1PIO8FPGA/CPLDÄ¿±êоƬPIO15-PIO8PIO7PIO6PIO5PIO4PIO3PIO2PIO1PIO0D16D15D14D13D12D11D10D9¼ü8¼ü7¼ü6¼ü5¼ü4¼ü3¼ü2¼ü1ʵÑéµç·½á¹¹Í¼NO.3SPEAKERÒëÂëÆ÷ÒëÂëÆ÷ÒëÂëÆ÷ÒëÂëÆ÷ÒëÂëÆ÷ÒëÂëÆ÷ÒëÂëÆ÷ÒëÂëÆ÷
附图2-5 实验电路结构图NO.3
附图2-6 实验电路结构图NO.4
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29C040(PIN31->WE,PIN1->A18,PIN30->A17,PIN3->A15,PIN29->A14)27040(PIN31->A18,PIN30->A17,PIN3->A15,PIN29->A14)27020(PIN30->A17,PIN3->A15,PIN29->A14)27010(PIN30->VCC,PIN3->A15,P29->A14)PIO48PIO10PIO47PIO14PIO39PIO38PIO37PIO36PIO35PIO34PIO33PIO32PIO24PIO25PIO26GNDVCC10KVR1PIO35PIO8PIO37C3010212345678910111213141516A18/A19VCCA16A18/A15/WEA14(A15)A17/VCCA12WR/A146264A7A1362256A6A8628128A5A92764A4A1127256A3OE27512A2A1027010A1CS127020A0D727040D0D627080D1D5D2D4GNDD3RAM/ROM32313029282726252423222120191817VCCPIO9PIO46PIO45PIO11PIO12PIO13PIO8PIO15PIO31PIO30PIO29PIO28PIO27PIO49VCCSLA17VCCSLRAM628128(PIN30->VCC,PIN3->A14,PIN29->WE)6264(PIN30->VCC,PIN29->WR)62256(PIN30->VCC,PIN3->A14,P29->WE)27512(PIN30->VCC,PIN3->A15,P29->A14)6J6178VGA24 视频接口35101314R76 200PIO40R77 200R78 200PIO41PIO42PIO43PIO44GNDRAM_ENVCC4513J7PS/2接口串行通讯接口53212MHZAPIO11PIO12PIO13PIO14PIO15PIO24PIO25PIO26PIO27PIO28PIO29PIO30PIO31VCC1112131415161718192010P37GND9P10P358P11P347P12P336P13P32EU35P14X14P15X23P16P312P17P301VCCRSTAT89C2051接PC机msb2-12-2EU1750KHZACLOCK2-310ADC08092-42-52-62-7AIN026lsb2-8IN-0727EOCIN-1JP2(5/6)25ADD-AAIN11ADD-B(24)0ADD-C(23)222ALE+5V912ENABLEref(+)166ref(-)STARTFITPIO46PIO45GND2468101214161820C29103B4RS-232接口电路135791113151719JP2ADENADEOCCOMPCOMM212019188151417PIO23PIO22PIO21PIO20PIO19PIO18PIO17PIO16PIO32PIO33PIO35PIO34PIO8复位键单片机接口电路FITJP2(1/2,3/4)87654321扬声器滤波1滤波0JP2COMM651031027.2K7TL082/2译码器译码器译码器译码器译码器译码器译码器译码器PIO19-PIO16PIO23-PIO20PIO27-PIO24PIO31-PIO28PIO35-PIO32PIO39-PIO36PIO43-PIO40PIO47-PIO44D8PIO15D7PIO14D6PIO13D5PIO12D4PIO11D3PIO10D2PIO9D1PIO8FPGA/CPLD目标芯片PIO15-PIO8PIO7PIO6PIO5PIO4PIO3PIO2PIO1PIO0SPEAKERAOUTR725.1K2WR1DAC08329EU2FBIOUT1IOUT2PIO24PIO25PIO26PIO27PIO28PIO29PIO30PIO31765416151413D0D1D2D3D4D5D6D7/CSWR2XFERA GNDD GND111211817310+1251pFC27234TL082/123LM311-12PIO3781VCCAIN010K+128D16D15D14D13D12D11D10D9键8键7键6键5键4键3键2键1实验电路结构图NO.58VREF20VCCVCC4-12COMPJP2(COMP)+5
附图2-7 实验电路结构图NO.5
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附图2-8 实验电路结构图NO.6
87654321扬声器译码器译码器译码器译码器译码器译码器PIO19-PIO16PIO23-PIO20PIO27-PIO24PIO31-PIO28PIO35-PIO32PIO39-PIO36D8PIO47D7PIO46D6PIO45D5PIO44D4PIO43D3PIO42D2PIO41D1PIO40FPGA/CPLD目标芯片PIO47-PIO40PIO7PIO6PIO5PIO4PIO3PIO2PIO0D16D15D14D13D12D11D9单脉冲单脉冲键8键7键6键5单脉冲键4键3键2键1实验电路结构图NO.7SPEAKER
附图2-9 实验电路结构图NO.7
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附图2-10 实验电路结构图NO.8
附图2-11 实验电路结构图NO.9
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附图2-12 实验电路结构图NO.B
PIO68PIO69PIO70PIO71PIO76PIO77PIO60PIO61PIO62PIO63PIO64PIO65PIO66PIO67abcdefgh数码9数码10数码11数码12数码13数码14888888GNDD+（PIO77）D-（PIO76）VCCUSBSLAVE10K X 4键10键9键11键12PIO73VCC24C011234GND8765VCCSCL（PIO78）SDA（PIO79）PIO72PIO74PIO75VCC654PS/2321GNDPIO76D22PIO77D21D20D19D18D17
附图2-13 实验电路结构图COM
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万能接插口与结构图信号/与芯片引脚对照表
EP1C3T144C 引脚名称 引脚号 引脚名称 引脚号 引脚名称 引脚号 PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 PIO28 1 2 3 4 5 6 7 10 11 32 33 34 35 36 37 38 39 40 41 42 47 48 49 50 51 52 67 68 69 PIO29 PIO30 PIO31 PIO32 PIO33 PIO34 PIO35 PIO36 PIO37 PIO38 PIO39 PIO40 PIO41 PIO42 PIO43 PIO44 PIO45 PIO46 PIO47 PIO48 PIO49 PIO60 PIO61 PIO62 PIO63 PIO64 PIO65 PIO66 PIO67 70 71 72 73 74 75 76 77 78 83 84 85 96 97 98 99 103 105 106 107 108 131 132 133 134 139 140 141 142 PIO68 PIO69 PIO70 PIO71 PIO72 PIO73 PIO74 PIO75 PIO76 PIO77 PIO78 PIO79 SPKER CLOCK0 CLOCK2 CLOCK5 CLOCK9 122 121 120 119 114 113 112 111 143 144 110 109 129 123/93 124/17 125/16 128/92 8
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附录二：《EDA技术》部分实验参考源程序
一、8位硬件加法器 设计程序如下： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER8 IS
PORT ( CIN : IN STD_LOGIC;
A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); COUT : OUT STD_LOGIC ); END ADDER8;
ARCHITECTURE behav OF ADDER8 IS
SIGNAL SINT : STD_LOGIC_VECTOR(8 DOWNTO 0); BEGIN
SINT <= ('0'& A) + B + CIN ;
S <= SINT(7 DOWNTO 0); COUT <= SINT(8); END behav;
选择实验电路NO.1验证此加法器的功能。
二、含异步清0和同步时钟使能的4位加法计数器程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT4B IS
PORT (CLK : IN STD_LOGIC; RST : IN STD_LOGIC; ENA : IN STD_LOGIC; OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT4B;
ARCHITECTURE behav OF CNT4B IS
SIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
P_REG: PROCESS(CLK, RST, ENA) 三、7段数码显示译码器设计程序
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LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DecL7S IS
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ; END ;
ARCHITECTURE one OF DecL7S IS BEGIN
PROCESS( A ) BEGIN
CASE A(3 DOWNTO 0) IS
WHEN \"0000\" => LED7S <= \"0111111\" ; -- X“3F”0 WHEN \"0001\" => LED7S <= \"0000110\" ; -- X“06”1 WHEN \"0010\" => LED7S <= \"1011011\" ; -- X“5B”2 WHEN \"0011\" => LED7S <= \"1001111\" ; -- X“4F”3 WHEN \"0100\" => LED7S <= \"1100110\" ; -- X“66”4 WHEN \"0101\" => LED7S <= \"1101101\" ; -- X“6D”5 WHEN \"0110\" => LED7S <= \"1111101\" ; -- X“7D”6 WHEN \"0111\" => LED7S <= \"0000111\" ; -- X“07”7 WHEN \"1000\" => LED7S <= \"1111111\" ; -- X“7F”8 WHEN \"1001\" => LED7S <= \"1101111\" ; -- X“6F”9 WHEN \"1010\" => LED7S <= \"1110111\" ; -- X“77”10 WHEN \"1011\" => LED7S <= \"1111100\" ; -- X“7C”11 WHEN \"1100\" => LED7S <= \"0111001\" ; -- X“39”12 WHEN \"1101\" => LED7S <= \"1011110\" ; -- X“5E”13 WHEN \"1110\" => LED7S <= \"1111001\" ; -- X“79”14 WHEN \"1111\" => LED7S <= \"1110001\" ; -- X“71”15 WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ;
四、数控分频器的设计程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PULSE IS
PORT ( CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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FOUT : OUT STD_LOGIC ); END;
ARCHITECTURE one OF PULSE IS SIGNAL FULL : STD_LOGIC; BEGIN
P_REG: PROCESS(CLK)
VARIABLE CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
IF CLK'EVENT AND CLK = '1' THEN IF CNT8 = \"11111111\" THEN
CNT8 := D; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8 FULL <= '1'; --同时使溢出标志信号FULL输出为高电平 ELSE CNT8 := CNT8 + 1; --否则继续作加1计数
FULL <= '0'; --且输出溢出标志信号FULL为低电平 END IF;
END IF;
END PROCESS P_REG ; P_DIV: PROCESS(FULL) VARIABLE CNT2 : STD_LOGIC; BEGIN
IF FULL'EVENT AND FULL = '1'
THEN CNT2 := NOT CNT2;--如果溢出标志信号FULL为高电平，D触发器输出取反 IF CNT2 = '1' THEN FOUT <= '1'; ELSE FOUT <= '0'; END IF; END IF;
END PROCESS P_DIV ; END;
五、4位十进制频率计设计程序 LIBRARY IEEE; --测频控制器 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY TESTCTL IS
PORT ( CLKK : IN STD_LOGIC; -- 1Hz CNT_EN,RST_CNT,LOAD : OUT STD_LOGIC); END TESTCTL;
ARCHITECTURE behav OF TESTCTL IS SIGNAL DIV2CLK : STD_LOGIC;
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BEGIN
PROCESS( CLKK ) BEGIN
IF CLKK'EVENT AND CLKK = '1' THEN DIV2CLK <= NOT DIV2CLK; END IF; END PROCESS;
PROCESS (CLKK, DIV2CLK) BEGIN
IF CLKK='0' AND Div2CLK='0' THEN RST_CNT <= '1'; ELSE RST_CNT <= '0'; END IF; END PROCESS;
LOAD <= NOT DIV2CLK ; CNT_EN <= DIV2CLK; END behav;
********************************** LIBRARY IEEE; --4位锁存器 USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG4B IS
PORT ( LOAD : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END REG4B;
ARCHITECTURE behav OF REG4B IS BEGIN
PROCESS(LOAD, DIN) BEGIN
IF LOAD'EVENT AND LOAD = '1' THEN DOUT <= DIN; --时钟到来时，锁存输入数据 END IF; END PROCESS; END behav;
六、状态机实现序列检测器的设计程序 【例6-27】 LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY SCHK IS
PORT( DIN，CLK，CLR : IN STD_LOGIC ; --串行输入数据位/工作时钟/复位信号
AB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --检测结果输出 END SCHK;
ARCHITECTURE behav OF SCHK IS
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SIGNAL Q : INTEGER RANGE 0 TO 8 ;
SIGNAL D : STD_LOGIC_VECTOR(7 DOWNTO 0); --8位待检测预置数 BEGIN
D <= \"11100101 \" ; --8位待检测预置数 PROCESS( CLK, CLR ) BEGIN
IF CLR = '1' THEN Q <= 0 ; CASE Q IS
WHEN 0=> IF DIN = D(7) THEN Q <= 1 ; ELSE Q <= 0 ; END IF ; WHEN 1=> IF DIN = D(6) THEN Q <= 2 ; ELSE Q <= 0 ; END IF ; WHEN 2=> IF DIN = D(5) THEN Q <= 3 ; ELSE Q <= 0 ; END IF ; WHEN 3=> IF DIN = D(4) THEN Q <= 4 ; ELSE Q <= 0 ; END IF ; WHEN 4=> IF DIN = D(3) THEN Q <= 5 ; ELSE Q <= 0 ; END IF ; WHEN 5=> IF DIN = D(2) THEN Q <= 6 ; ELSE Q <= 0 ; END IF ; WHEN 6=> IF DIN = D(1) THEN Q <= 7 ; ELSE Q <= 0 ; END IF ; WHEN 7=> IF DIN = D(0) THEN Q <= 8 ; ELSE Q <= 0 ; END IF ; WHEN OTHERS => Q <= 0 ; END CASE ; END IF ; END PROCESS ;
PROCESS( Q ) --检测结果判断输出 BEGIN
IF Q = 8 THEN AB <= \"1010\" ; --序列数检测正确，输出 “A” ELSE AB <= \"1011\" ; --序列数检测错误，输出 “B” END IF ; END PROCESS ; END behav ;
提示：若对于D <= \"11100101 \"，电路需记忆：初始状态、1、11、111 、 1110 、11100、111001、1110010、11100101 共9种状态。 七、用状态机对ADC0809的采样控制电路实现 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADCINT IS
PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --0809的8位转换数据输出 CLK ,EOC : IN STD_LOGIC; --CLK是转换工作时钟 LOCK1, ALE, START, OE, ADDA : OUT STD_LOGIC;
ELSIF CLK'EVENT AND CLK='1' THEN --时钟到来时，判断并处理当前输入的位
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Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ADCINT;
ARCHITECTURE behav OF ADCINT IS
TYPE states IS (st0, st1, st2, st3,st4,st5,st6) ; --定义各状态子类型 SIGNAL current_state, next_state: states :=st0 ; SIGNAL REGL BEGIN
ADDA <= '1'; LOCK1 <=LOCK;
PRO: PROCESS(current_state,EOC) BEGIN --规定各状态转换方式 CASE current_state IS
WHEN st0 => ALE<='0';START<='0';OE<='0';LOCK<='0' ;next_state <= st1; WHEN st1 => ALE<='1';START<='0';OE<='0';LOCK<='0' ;next_state <= st2;
WHEN st2 => ALE<='0';START<='1';OE<='0';LOCK<='0' ;next_state <= st3; WHEN st3 => ALE<='0';START<='0';OE<='0';LOCK<='0'; IF (EOC='1') THEN next_state <= st3; --测试EOC的下降沿
ELSE next_state <= st4; END IF ;
WHEN st4=> ALE<='0';START<='0';OE<='0';LOCK<='0';
IF (EOC='0') THEN next_state <= st4; --测试EOC的上升沿，=1表明转换结束
ELSE next_state <= st5; --继续等待 END IF ;
WHEN st5=> ALE<='0';START<='0';OE<='1';LOCK<='0';next_state <= st6; WHEN OTHERS => ALE<='0';START<='0';OE<='0';LOCK<='0';next_state <= st0; END CASE ; END PROCESS PRO ; PROCESS (CLK) BEGIN
IF ( CLK'EVENT AND CLK='1') THEN
current_state <= next_state; -- 在时钟上升沿，转换至下一状态 END IF;
END PROCESS; -- 由信号current_state将当前状态值带出此进程，进入进程PRO PROCESS (LOCK) -- 此进程中，在LOCK的上升沿，将转换好的数据锁入 BEGIN
IF LOCK='1' AND LOCK'EVENT THEN REGL <= D ; END IF; END PROCESS ;
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: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK : STD_LOGIC; -- 转换后数据输出锁存时钟信号
WHEN st6=> ALE<='0';START<='0';OE<='1';LOCK<='1';next_state <= st0;
Q <= REGL; END behav;
八、硬件电子琴电路设计程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY Speaker IS
PORT ( clk1 : IN STD_LOGIC;
Tone1 : IN INTEGER RANGE 0 TO 16#7FF#; SpkS : OUT STD_LOGIC ); END;
ARCHITECTURE one OF Speaker IS
SIGNAL PreCLK , FullSpkS : STD_LOGIC; BEGIN
DivideCLK : PROCESS(clk1)
VARIABLE Count4 : INTEGER RANGE 0 TO 15; BEGIN
PreCLK <= '0'; -- 将CLK进 11分频，PreCLK为C L 11K 6分频 IF Count4 > 11 THEN PreCLK <= '1'; Count4 := 0;
ELSIF clk1'EVENT AND clk1='1' THEN Count4 := Count4 + 1; END IF; END PROCESS;
GenSpkS : PROCESS(PreCLK, Tone1)
VARIABLE Count11 : INTEGER RANGE 0 TO 16#7FF#; BEGIN -- 11位可预置计数器 IF PreCLK'EVENT AND PreCLK = '1' THEN
IF Count11=16#7FF# THEN Count11 := Tone1; FullSpkS <= '1'; ELSE Count11:=Count11 + 1; FullSpkS <= '0'; END IF; END IF; END PROCESS;
DelaySpkS : PROCESS(FullSpkS) VARIABLE Count2 : STD_LOGIC; BEGIN
IF FullSpkS'EVENT AND FullSpkS = '1' THEN Count2 := NOT Count2; IF Count2 = '1' THEN SpkS <= '1'; ELSE SpkS <= '0';
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END IF; END IF; END PROCESS; END;
********************************************************** LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY Tone IS
PORT ( Index : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE : OUT INTEGER RANGE 0 TO 15; HIGH : OUT STD_LOGIC;
Tone : OUT INTEGER RANGE 0 TO 16#7FF# ); END;
ARCHITECTURE one OF Tone IS BEGIN
Search : PROCESS(Index) BEGIN
CASE Index IS -- 译码电路，查表方式，控制音调的预置数 WHEN \"00000001\" => Tone <= 773; CODE <= 1; HIGH <= '0'; WHEN \"00000010\" => Tone <= 912; CODE <= 2; HIGH <= '0'; WHEN \"00000100\" => Tone <= 1036; CODE <= 3; HIGH <= '0'; WHEN \"00001000\" => Tone <= 1116; CODE <= 4; HIGH <= '0'; WHEN \"00010000\" => Tone <= 1197; CODE <= 5; HIGH <= '0'; WHEN \"00100000\" => Tone <= 1290; CODE <= 6; HIGH <= '0'; WHEN \"01000000\" => Tone <= 1372; CODE <= 7; HIGH <= '0'; WHEN \"10000000\" => Tone <= 1410; CODE <= 1; HIGH <= '1'; WHEN OTHERS => Tone <= 2047; CODE <= 0; HIGH <= '0'; END CASE; END PROCESS; END;
******************************************************************* LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS -- 顶层设计 PORT ( CLK12MHZ : IN STD_LOGIC;
INDEX1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE1 : OUT INTEGER RANGE 0 TO 15; HIGH1,SPKOUT : OUT STD_LOGIC );
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END;
ARCHITECTURE one OF TOP IS COMPONENT Tone
PORT ( Index : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE : OUT INTEGER RANGE 0 TO 15; HIGH : OUT STD_LOGIC;
Tone : OUT INTEGER RANGE 0 TO 16#7FF# ); --11位2进制数 END COMPONENT; COMPONENT Speaker
PORT ( clk1 : IN STD_LOGIC;
Tone1 : IN INTEGER RANGE 0 TO 16#7FF#; --11位2进制数 SpkS : OUT STD_LOGIC ); END COMPONENT;
SIGNAL Tone2 : INTEGER RANGE 0 TO 16#7FF#; BEGIN -- 安装U1, U2
u1 : Tone PORT MAP (Index=>Index1, Tone=>Tone2,CODE=>CODE1,HIGH=>HIGH1); u2 : Speaker PORT MAP (clk1=>CLK12MHZ,Tone1=>Tone2, SpkS=>SPKOUT ); END;
九、波形发生与扫频信号发生器电路设计程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DAC IS
PORT ( CLK,CLK1,KK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); DD : OUT INTEGER RANGE 255 DOWNTO 0 ); END;
ARCHITECTURE DACC OF DAC IS
SIGNAL Q : INTEGER RANGE 63 DOWNTO 0 ; SIGNAL D : INTEGER RANGE 255 DOWNTO 0 ; SIGNAL FSS : STD_LOGIC ;
SIGNAL COUNT12,DATA2,DATA1 : STD_LOGIC_VECTOR(11 DOWNTO 0) ; BEGIN
PROCESS(FSS) BEGIN
IF (FSS'EVENT AND FSS = '1') THEN Q <= Q + 1; END IF;
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END PROCESS; PROCESS(Q) BEGIN
CASE Q IS
WHEN 00=> D<=255; WHEN 01=> D<=254; WHEN 02=> D<=252; WHEN 03=> D<=249; WHEN 04=> D<=245; WHEN 05=> D<=239; WHEN 06=> D<=233; WHEN 07=> D<=225; WHEN 08=> D<=217; WHEN 09=> D<=207; WHEN 10=> D<=197; WHEN 11=> D<=186; WHEN 12=> D<=174; WHEN 13=> D<=162; WHEN 14=> D<=150; WHEN 15=> D<=137; WHEN 16=> D<=124; WHEN 17=> D<=112; WHEN 18=> D<= 99; WHEN 19=> D<= 87; WHEN 20=> D<= 75; WHEN 21=> D<= 64; WHEN 22=> D<= 53; WHEN 23=> D<= 43; WHEN 24=> D<= 34; WHEN 25=> D<= 26; WHEN 26=> D<= 19; WHEN 27=> D<= 13; WHEN 28=> D<= 8; WHEN 29=> D<= 4; WHEN 30=> D<= 1; WHEN 31=> D<= 0; WHEN 32=> D<= 0; WHEN 33=> D<= 1; WHEN 34=> D<= 4; WHEN 35=> D<= 8; WHEN 36=> D<= 13; WHEN 37=> D<= 19; WHEN 38=> D<= 26; WHEN 39=> D<= 34; WHEN 40=> D<= 43; WHEN 41=> D<= 53; WHEN 42=> D<= 64; WHEN 43=> D<= 75; WHEN 44=> D<= 87; WHEN 45=> D<= 99; WHEN 46=> D<=112; WHEN 47=> D<=124; WHEN 48=> D<=137; WHEN 49=> D<=150; WHEN 50=> D<=162; WHEN 51=> D<=174; WHEN 52=> D<=186; WHEN 53=> D<=197; WHEN 54=> D<=207; WHEN 55=> D<=217; WHEN 56=> D<=225; WHEN 57=> D<=233; WHEN 58=> D<=239; WHEN 59=> D<=245; WHEN 60=> D<=249; WHEN 61=> D<=252; WHEN 62=> D<=254; WHEN 63=> D<=255; WHEN OTHERS => NULL ; END CASE; END PROCESS; DD <= D ;
PROCESS(CLK, DATA) BEGIN
IF CLK'EVENT AND CLK = '1' THEN
IF COUNT12 = \"111111100000\" THEN COUNT12 <= DATA1; FSS <= '1'; ELSE COUNT12 <= COUNT12 + 1; FSS <= '0'; END IF; END IF; END PROCESS;
DATA1 <= DATA WHEN KK = '1' ELSE
DATA2 WHEN KK = '0' ELSE DATA2 ; PROCESS(CLK1) BEGIN
IF (CLK1'EVENT AND CLK1 = '1') THEN DATA2 <= DATA2 + 1; END IF;
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END PROCESS; END;
十、移位相加8位硬件乘法器电路设计程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SREG8B IS -- 8位右移寄存器 PORT ( CLK : IN STD_LOGIC; LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC ); END SREG8B;
ARCHITECTURE behav OF SREG8B IS
SIGNAL REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
PROCESS (CLK, LOAD) BEGIN
IF LOAD = '1' THEN REG8 <= DIN; ELSIF CLK'EVENT AND CLK = '1' THEN REG8(6 DOWNTO 0) <= REG8(7 DOWNTO 1); END IF; END PROCESS;
QB <= REG8(0); -- 输出最低位 END behav;
********************************************************* LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER8 IS
PORT(B, A : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) ); END ADDER8;
ARCHITECTURE behav OF ADDER8 IS BEGIN
S <= '0'&A + B ; END behav;
************************************************************ LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ANDARITH IS -- 选通与门模块 PORT ( ABIN : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ANDARITH;
ARCHITECTURE behav OF ANDARITH IS BEGIN
PROCESS(ABIN, DIN) BEGIN
FOR I IN 0 TO 7 LOOP -- 循环，完成8位与1位运算 DOUT(I) <= DIN(I) AND ABIN; END LOOP; END PROCESS; END behav;
*********************************************************** LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG16B IS PORT ( CLK,CLR : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END REG16B;
ARCHITECTURE behav OF REG16B IS
SIGNAL R16S : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN
PROCESS(CLK, CLR) BEGIN
IF CLR = '1' THEN R16S <= (OTHERS =>'0') ; -- 清零信号
ELSIF CLK'EVENT AND CLK = '1' THEN -- 时钟到来时，锁存输入值，并右移低8 R16S(6 DOWNTO 0) <= R16S(7 DOWNTO 1); -- 右移低8位 R16S(15 DOWNTO 7) <= D; -- 将输入锁到高8位 END IF; END PROCESS; Q <= R16S; END behav;
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