CDP6402资料

SEMICONDUCTOR

CDP6402,CDP6402CCMOS Universal AsynchronousReceiver/Transmitter (UART)

DescriptionThe CDP6402 and CDP6402C are silicon gate CMOSUniversal Asynchronous Receiver/Transmitter (UART)circuits for interfacing computers or microprocessors toasynchronous serial data channels. They are designed toprovide the necessary formatting and control for interfacingbetween serial and parallel data channels. The receiverconverts serial start, data, parity, and stop bits to paralleldata verifying proper code transmission, parity and stop bits.The transmitter converts parallel data into serial form andautomatically adds start parity and stop bits.The data word can be 5, 6, 7 or 8 bits in length. Parity maybe odd, even or inhibited. Stop bits can be 1, 1-1/2, or 2(when transmitting 5-bit code).The CDP6402 and CDP6402C can be used in a wide rangeof applications including modems, printers, peripherals,video terminals, remote data acquisition systems, and serialdata links for distributed processing systems.The CDP6402 and CDP6402C are functionally identical.They differ in that the CDP6402 has a recommendedoperating voltage range of 4V to 10.5V, and the CDP6402Chas a recommended operating voltage range of 4V to 6.5V.August 1996

Features•Low Power CMOS Circuitry. . . . . . . . . .7.5mW (Typ) at3.2MHz (Max Freq.) at VDD = 5V•Baud Rate-DC to 200K Bits/s (Max) at. . . . . . . . . . . . . . 5V, 85oC-DC to 400K Bits/s (Max) at. . . . . . . . . . . . . .10V, 85oC•4V to 10.5 Operation•Automatic Data Formatting and Status Generation•Fully Programmable with Externally Selectable WordLength (5 - 8 Bits), Parity Inhibit, Even/Odd Parity, and1,1-1/2, or 2 Stop Bits•Operating Temperature Range-CDP6402D, CD . . . . . . . . . . . . . . . . .-55oC to +125oC-CDP6402E, CE . . . . . . . . . . . . . . . . . .-40oC to +85oC•Replaces Industry Type IM6402 and Compatible withHD6402Ordering InformationPACK-AGEPDIPBurn-InSBDIPBurn-In-40oC to +85oCTEMP. RANGE-40oC to +85oC5V/200KBAUDCDP6402CECDP6402CEXCDP6402CD10V/400KBAUDCDP6402E-CDP6402DPKG.NO.E40.6D40.6CDP6402CDXCDP6402DXPinout(40 LEAD PDIP, SBDIP)TOP VIEWVDDNCGNDRRDRBR8RBR7RBR6RBR5RBR4RBR3RBR2RBR1PEFEOESFDRRCDRRDRRRI12345678910111213141516171819204039383736353433323130292827262524232221TRCEPECLS1CLS2SBSPICRLTBR8TBR7TBR6TBR5TBR4TBR3TBR2TBR1TROTRETBRLTBREMRCAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.Copyright © Harris Corporation 1996

File Number

1328.2

5-74

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CDP6402, CDP6402CTBR8 (MSB)TBR1 (LSB)TRETBRLTRCPARITYLOGICTRANSMITTER BUFFER REGISTERTRANSMITTERTIMINGANDCONTROLSTOPTRANSMITTER REGISTERMULTIPLEXERTROCONTROLREGISTERSBSEPEPISTARTCLS1CLS2CRLMRRRCDRRRRIRECEIVERTIMINGANDCONTROLSTOPLOGICPARITYLOGICMULTIPLEXERRECEIVER REGISTERRECEIVER BUFFER REGISTERTHREESTATEBUFFERSSTARTLOGICSFDRRDDROETBREFEPERBR8 (MSB)RBR1 (LSB)FIGURE 1.FUNCTIONAL BLOCK DIAGRAM5-75

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CDP6402, CDP6402CAbsolute Maximum RatingsDC Supply-Voltage Range, (VDD)CDP6402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +11VCDP6402C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7VInput Voltage Range, All Inputs . . . . . . . . . . . . . .-0.5 to VDD +0.5VDC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . .±100µADevice Dissipation Per Output TransistorFor TA = Full Package-Temperature Range(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mWOperating-Temperature Range (TA)Package Type D (SBDIP) . . . . . . . . . . . . . . . . . .-55oC to +125oCPackage Type E (PDIP) . . . . . . . . . . . . . . . . . . . .-40oC to +85oCThermal InformationThermal Resistance (Typical, Note 1)θJA (oC/W)θJC (oC/W)PDIP Package. . . . . . . . . . . . . . . . . . .50N/ASBDIP Package. . . . . . . . . . . . . . . . . . 5515oMaximum Storage Temperature Range (TSTG) . . .-65C to +150oCMaximum Lead Temperature (Soldering 10s):At Distance 1/16±1/32 inch (1.59±0.79mm) . . . . . . . . . .+265oCCAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation ofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied.NOTE:1.θJA is measured with the component mounted on an evaluation PC board in free air.Operating ConditionsAt TA = Full Package-Temperature Range. For maximum reliability, operating conditions should be selected sothat operatIon is always within the following ranges: LIMITSCDP6402PARAMETERDC Operating Voltage RangeInput Voltage RangeMIN4VSSMAX10.5VDDMIN4VSSCDP6402CMAX6.5VDDUNITSVVStatic Electrical Specificationsat TA = -40oC to +85oC, VDD±10%, Except as notedCONDITIONSCDP6402VO(V)IDD--Output Low Drive(Sink) CurrentIOL0.40.5Output High Drive(Source) CurrentIOH4.69.5Output Voltage Low-Level (Note 2)VOL--Output VoltageHigh Level (Note 2)VOH--Input Low VoltageVIL0.5, 4.50.5, 9.5VIN(V)0, 50,100,50,100, 50,100, 50, 100, 50, 10--VDD(V)510510510510510510(NOTE 1)TYP0.01147-1.1-2.600510--LIMITSCDP6402C(NOTE 1)TYP0.02-2.4--1.1-0-5---PARAMETERQuiescent DeviceCurrentMIN--25-0.55-1.3--4.99.9--MAX50200----0.10.1--0.80.2 VDDMIN--1.2--0.55---4.9---MAX200-----0.1---0.8-UNITSµAµAmAmAmAmAVVVVVV5-76

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CDP6402, CDP6402CStatic Electrical Specificationsat TA = -40oC to +85oC, VDD±10%, Except as noted (Continued)CONDITIONSCDP6402VO(V)VIH0.5, 4.50.5, 9.5Input LeakageCurrentIINAnyInputVIN(V)--0,50,10Three-State OutputLeakage CurrentIOUT0, 50, 10Operating Current(Note 2)IDD1--Input CapacitanceOutput CapacitanceNOTES:1.Typical values are for TA= 25oC and nominal VDD2.IOL = IOH = 1µA.3.Operating current is measured at 200kHz or VDD = 5V and 400kHz for VDD = 10V, with open outputs (worst-case frequencies forCDP1802A system operating at maximum speed of 3.2MHz).CINCOUT--0, 50,100, 50,10--VDD(V)510510510510--(NOTE 1)TYP--±10-4±10-4±10-4±10-41.510510LIMITSCDP6402C(NOTE 1)TYP----±10-4-1.5-510PARAMETERInput High VoltageMINVDD-27--------MAX--±1±2±1±10−−7.515MINVDD-2---------MAX--±1-±1---7.515UNITSVVµAµAµAµAmAmApFpF5-77

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CDP6402, CDP6402CDescription of OperationInitialization and ControlsA positive pulse on the MASTER RESET (MR) input resetsthe control, status, and receiver buffer registers, and sets theserial output (TRO) High. Timing is generated from the clockinputs RRC and TRC at a frequency equal to 16 times theserial data bit rate. The RRC and TRC inputs may be drivenby a common clock, or may be driven independently by twodifferent clocks. The CONTROL REGISTER LOAD (CRL)input is strobed to load control bits for PARITY INHIBIT (PI),EVEN PARITY ENABLE (EPE), STOP BIT SELECTS (SBS),and CHARACTER LENGTH SELECTS (CLS1 and CLS2).These inputs may be hand wired to VSSor VDD with CRL toVDD. When the initialization is completed, the UART is readyfor receiver and/or transmitter operations.Transmitter OperationThe transmitter section accepts parallel data, formats it, andtransmits it in serial form (Figure 2) on the TRO terminal.STARTBITLSB5 - 8 DATA BITS1, 1-1/2 OR2 STOP BITSFE, PEABC1/2 CLOCKCYCLESReceiver OperationData is received in serial form at the RRl input. When nodata is being received, RRI input must remain high. The datais clocked through the RRC. The clock rate is 16 times thedata rate. Receiver timing is shown in Figure 4.BEGINNING OF FIRST STOP BITRRIRBRI-8, OEDRR8 1/2 TO 9 1/2CLOCK CYCLESDRFIGURE 4.RECEIVER TIMING WAVEFORMSMSB†PARITY† IF ENABLEDFIGURE 2.SERIAL DATA FORMATTransmitter timing is shown in Figure 3. (A) Data is loadedinto the transmitter buffer register from the inputs TBR1through TBR8 by a logic low on theTBRL input. Valid datamust be present at least tDTprior to, and tTD following, therising edge ofTBRL. If words less than 8-bits are used, onlythe least significant bits are used. The character is right justi-fied into the least significant bit, TBR1. (B) The rising edge ofTBRL clears TBRE. 1/2 to 11/2 cycles later, depending onwhen theTBRL pulse occurs with respect to TRC, data istransferred to the transmitter register and TRE is cleared.TBRE is set to a logic High one cycle after that.Output data is clocked by TRC. The clock rate is 16 timesthe data rate. (C) A second pulse onTBRL loads data intothe transmitter buffer register. Data transfer to the transmitterregister is delayed until transmission of the current characteris complete. (D) Data is automatically transferred to thetransmitter register and transmission of that characterbegins.TBRL(A) A low level onDRR clears the DR line. (B) During the firststop bit data is transferred from the receiver register to theRB Register. If the word is less than 8 bits, the unused mostsignificant bits will be a logic low. The output character isright justified to the least significant bit RBR1. A logic high onOE indicates overruns. An overrun occurs when DR has notbeen cleared before the present character was transferred tothe RBR. (C) 1/2 clock cycle later DR is set to a logic highand FE is evaluated. A logic high on FE indicates an invalidstop bit was received. A logic high on PE indicates a parityerror.Start Bit DetectionThe receiver uses a 16X clock for timing (Figure 5). The startbit could have occurred as much as one clock cycle before itwas detected, as indicated by the shaded portion. The cen-ter of the start bit is defined as clock count 7 1/2. If thereceiver clock is a symmetrical square wave, the center ofthe start bit will be located within±1/2 clock cycle±1/32 bit or±3.125%. The receiver begins searching for the next start bitat 9 clocks into the first stop bit.COUNT 7 1/2DEFINED CENTEROF START BITCLOCKTBRE1-1/2 TO 2-1/2 CYCLESTRETROAB1/2 TO 1-1/2 CYCLES1 TO 2 CYCLESDATACDEND OFLASTSTOP BIT1/2CLOCKRRIINPUTASTART7 1/2 CLOCKCYCLES8 1/2 CLOCKCYCLESFIGURE 3.TRANSMITTER TIMING WAVEFORMSFIGURE 5.START BIT TIMING WAVEFORMS5-78

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CDP6402, CDP6402CTABLE 1.CONTROL WORD FUNCTIONCONTROL WORDCLS2LLLLLLLLLLLLHHHHHHHHHHHHNOTE:X = Don’t CareCLS1LLLLLLHHHHHHLLLLLLHHHHHHPILLLLHHLLLLHHLLLLHHLLLLHHEPELLHHXXLLHHXXLLHHXXLLHHXXSBSLHLHLHLHLHLHLHLHLHLHLHLHDATA BITS5555PARITY BITODDODD EVEN EVENSTOP BIT (S)11.511.511.5121212121212121212 5DISABLED566DISABLEDODD ODD 6 EVEN666 EVENDISABLEDDISABLED 7ODD77 ODD EVEN7 EVEN 7DISABLED7888888DISABLEDODD ODD EVEN EVENDISABLEDDISABLED5-79

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CDP6402, CDP6402CTABLE 2.FUNCTION PIN DEFINITIONPIN1234SYMBOLVDDN/CGNDRRDPositive Power SupplyNo ConnectionGround (VSS)A high level on RECEIVER REGISTER DISABLE forces the receiver holding register ouputs RBR1-RBR8 toa high impedance state.The contents of the RECEIVER BUFFER REGISTER appear on these three-state outputs. Word formats lessthan 8 characters are right justified to RBR1.DESCRIPTION5RBR8678910111213RBR7RBR6RBR5RBR4RBR3RBR2RBR1 PEA high level on PARITY ERROR indicates that the received parity does not match parity programmed by controlbits. The output is active until parity matches on a succeeding character. When parity is inhibited, this outputis low.A high level on FRAMING ERROR indicates the first stop bit was invalid. FE will stay active until the next validcharacter’s stop bit is received.A high level on OVERRUN ERROR indicates the data received flag was not cleared before the last characterwas transferred to the receiver buffer register. The Error is reset at the next character’s stop bit if DRR has beenperformed (i.e., DRR; active low).A high level on STATUS FLAGS DISABLE forces the outputs PE, FE, OE, DR, TBRE to a high impedancestate.The RECEIVER REGISTER CLOCK is 16X the receiver data rate.A low level on DATA RECEIVED RESET clears the data received output (DR), to a low level.A high level on DATA RECEIVED indicates a character has been received and transferred to the receiver bufferregister.Serial data on RECEIVER REGISTER INPUT is clocked into the receiver register.A high level on MASTER RESET (MR) clears PE, FE, OE and DR, and sets TRE, TBRE, and TRO. TRE isactually set on the first rising edge of TRC after MR goes high. MR should be strobed after power-up.A high level on TRANSMITTER BUFFER REGISTER EMPTY indicates the transmitter buffer register hastransferred its data to the transmitter register and is ready for new data.A low level on TRANSMITTER BUFFER REGISTER LOAD transfers data from inputs TBR1-TBR8 into thetransmitter buffer register. A low to high transition onTBRL requests data transfer to the transmitter register. Ifthe transmitter register is busy, transfer is automatically delayed so that the two characters are transmitted endto end.A high level on TRANSMITTER REGISTER EMPTY indicates completed transmission of a character includingstop bits.See Pin 5 - RBR814 FE15OE16SFD171819RRCDRR DR2021RRl MR22TBRE23TBRL24TRE5-80

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CDP6402, CDP6402CTABLE 2.FUNCTION PIN DEFINITION (Continued)PIN2526SYMBOLTROTBR1DESCRIPTIONCharacter data, start data and stop bits appear serially at the TRANSMITTER REGISTER OUTPUT.Character data is loaded into the TRANSMITTER BUFFER REGISTER via inputs TBR1-TBR8. For characterformats less than 8 bits, the TBR8, 7, and 6 Inputs are ignored corresponding to the programmed word length.27282930313233343536TBR2TBR3TBR4TBR5TBR6TBR7TBR8CRL PI†SBS†A high level on CONTROL REGISTER LOAD loads the control register.A high level on PARITY INHIBIT inhibits parity generation, parity checking and forces PE output low.A high level on STOP BIT SELECT selects 1.5 stop bits for a 5 character format and 2 stop bits for otherlengths.These inputs program the CHARACTER LENGTH SELECTED. (CLS1 low CLS2 low 5 bits) (CLS1 high CLS2low 6 bits) (CLS1 low CLS2 high 7 bits) (CLS1 high CLS2 high 8 bits).See Pin 37 - CLS2When PI is low, a high level on EVEN PARITY ENABLE generates and checks even parity. A low level selectsodd parity.The TRANSMITTER REGISTER CLOCK is 16X the transmit data rate.See Pin 26 - TBR137CLS2†3839CLSl†EPE†40TRC†See Table 1 (Control Word Function)5-81

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CDP6402, CDP6402CDynamic Electrical Specificationsat TA = -40oC to +85oC, VDD±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pFLIMITSCDP6402(NOTE 1)PARAMETERSYSTEM TIMING (See Figure 6)Minimum Pulse WidthCRLMinimum Setup TimeControl Word to CRLMinimum Hold TimeControl Word after CRLPropagation Delay TimeSFD High to SODSFD Low to SODtCRL510 tCWC510tCCW510tSFDH510tSFDL510RRD High to Receiver RegisterHigh ImpedanceRRD Low to Receiver RegisterActiveMinimum Pulse WidthMRNOTES:1.All measurements are made at the 50% point of the transition except three-state measurements.2.Typical values for TA = 25oC and nominal VDD.3.Maximum limits of minimum characteristics are the values above which all devices function.tRRDH510 tRRDL5105105040200402013010013040804080402001001501005040603020015020060150701507040020050-20-40-130-130-80-80-200-150-50-60-200-200-150-150-400-nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsVDD(V)(NOTE 2)TYP(NOTE 3)MAXCDP6402C(NOTE 2)TYP(NOTE 3)MAXUNITSCONTROL INPUT WORD TIMINGCONTROL WORD INPUTCONTROL WORD BYTEtCWCCRLtCRLSTATUS OUTPUT TIMINGSTATUS OUTPUTStSFDHSFD90%10%70%30%tSFDLtCCWRECEIVER REGISTER DISCONNECT TIMING90%10%R BUS 7R BUS 0tRRDHRRD70%30%tRRDLFIGURE 6.SYSTEM TIMING WAVEFORMS5-82

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CDP6402, CDP6402CDynamic Electrical Specificationsat TA = -40oC to +85oC, VDD±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pFLIMITSCDP6402(NOTE 1)PARAMETERTRANSMITTER TIMING (See Figure 7)Minimum Clock Period (TRC)tCC510Minimum Pulse WidthClock Low LeveltCL510Clock High LeveltCH510TBRLtTHTH510Minimum Setup TimeTBRL to ClocktTHC510Data toTBRLtDT510Minimum Hold-Time Data after TBRLtTD510Propagation Delay TimeClock to Data Start BittCD510Clock to TBREtCT510TBRL to TBREtTTHR510Clock to TREtTTS510NOTES:1.All measurements are made at the 50% point of the transition except three-state measurements.2.Typical values for TA = 25oC and nominal VDD.3.Maximum limits of minimum characteristics are the values above which all devices function.300150330100200100330100450225400150300150400150300-330-200-330-450-400-300-400-nsnsnsnsnsnsnsns4020603040-60-nsns175902002751505040175-20-275-50-nsnsnsns10075100758040125100125100200100100-100-80-125-125-200-nsnsnsnsnsns250125310155250-310-nsnsVDD(V)(NOTE 2)TYP(NOTE 3)MAXCDP6402C(NOTE 2)TYP(NOTE 3)MAXUNITS5-83

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CDP6402, CDP6402CTRANSMITTER BUFFERREGISTER LOADED(NOTE 1)tCCtCHTRCtTHCTBRLtTHTHTROtTTHRTBREtTTSTRET BUS 0T BUS 7tDTDATAtDTtCTtCDtCD1ST DATA BITtCL1TRANSMITTER SHIFTREGISTER LOADED(NOTE 2)234567141516123NOTES:1.The holding register is loaded on the trailing edge ofTBRL.2.The transmitter shift register, if empty , is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period +tTHC after the trailing edge ofTBRL and transmission of a start bit occurs 1/2 clock period + tCD later.FIGURE 7.TRANSMITTER TIMING WAVEFORMStCCtCHRRCtDC(NOTE 1)RRIR BUS 0 -R BUS 7DRtCL1234CLOCK 7 1/2SAMPLE5671612CLOCK 7 1/2 LOADHOLDING REGISTER3456789START BIT PARITYSTOP BIT 1tCDVDATAtDDADRRtDDOE(NOTE 2)PEtCFEFEtCOEtCDAtCPENOTES:1.If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the nexthigh-to-low transition of the clock. The start bit may be completely asynchronous with the clock.2.If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holdingregister, the OE signal will come true..FIGURE 8.RECEIVER TIMING WAVEFORMS5-84

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CDP6402, CDP6402CDynamic Electrical Specificationsat TA = -40oC to +85oC, VDD±5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pFLIMITSCDP6402(NOTE 1)PARAMETERSRECEIVER TIMING (See Figure 8)Minimum Clock Period (RRC)tCC510Minimum Pulse WidthClock Low LeveltCL510Clock High LeveltCH510Data Received ResettDD510Minimum Setup Time Data Start Bit to ClocktDC510Propagation Delay TimeData Received Reset toData ReceivedtDDA510Clock to Data ValidtCDV510Clock to DR tCDA510Clock to Overrun ErrortCOE510Clock to Parity ErrortCPE510Clock to Framing ErrortCFE510NOTES:1.All measurements are made at the 50% point of the transition except three-state measurements.2.Typical values for TA = 25oC and nominal VDD.3.Maximum limits of minimum characteristics are the values above which all devices function.1507527511027511027510024012020010025012540017540017540015037517300150150-275-275-275-240-200-250-400-400-400-375-300-nsnsnsnsnsnsnsnsnsnsnsns1005015075100-150-nsns100751007550251251001251007540100-100-50-125-125-75-nsnsnsnsnsns250125310155250-310-nsnsVDD(V)(NOTE 2)TYP(NOTE 3)MAXCDP6402C(NOTE 2)TYP(NOTE 3)MAXUNITS5-85